Redundant CPU for deterministic control
The Q25PRHCPU is the redundant CPU in the MELSEC-Q [QnU] series, built for applications where a single CPU failure cannot stop the line. The 34 ns LD instruction and 102 ns MOV instruction define the scan floor — at 0.5 ms constant scan minimum, the CPU holds deterministic timing cycle after cycle, no jitter in the loop. Program capacity of 252K steps supports large machine sequences or process logic, and the 778 total instructions cover sequence control language and process control language. The memory card interface accepts SRAM, Flash, or ATA cards for program storage and backup.
Scan cycle and I/O refresh
Constant scan is settable from 0.5 to 2000 ms in 0.5 ms increments — the control method is stored program cyclic operation, so the scan time is predictable and repeatable. Floating point addition completes in 0.78 μs, and the PC MIX value of 10.3 (instruction/μs) gives a quick read on mixed-instruction throughput. I/O control mode is Refresh, meaning the CPU updates all I/O images in one batch per scan rather than direct access — this simplifies timing analysis for the controls integrator mapping the fieldbus slice.