CPU core and programming environment
The 6AG1211-0AA23-2XB0: This is the S7-200 CPU 221, the compact fixed-I/O member of the family. It supports LAD (ladder), FBD (function block diagram), and STL (statement list) programming, so any engineer familiar with the Siemens STEP 7-Micro/WIN environment can work with it without retooling. The program executes in a free cycle (OB 1), with interrupt control and time-controlled processing from 1 to 255 ms. The command set covers bit logic, timers, counters, integer and floating-point math, shift/rotate, table, and communications instructions.
I/O and signal conditioning
Eight digital inputs, configurable per group as source or sink, with a signal '1' threshold of min. 15 V and signal '0' from 0 to 5 V. Six of the inputs (E 0.0 to E 0.5) are parameterizable as high-speed counters at 30 kHz each. The six digital outputs include two pulse-train outputs (Q0.0, Q0.1) with a rise time of 2 µs and fall time of 10 µs — fast enough for simple stepper or PWM control. The four standard outputs (Q0.2 to Q0.3) switch in 15 µs on, 100 µs off. Total output current is 3 A up to 55 °C, with a 5 W lamp-load limit per channel.
Communication and networking
An integrated RS 485 interface supports both PPI and MPI protocols. PPI runs at 9.6/19.2/187.5 kbit/s for programming and HMI (TD 200, OP) communication, plus CPU-to-CPU data exchange within the S7-200 family. MPI operates at the same rates, allowing the CPU to act as an MPI slave to S7-300/S7-400 CPUs, OPs, and TDs. Maximum cable length is 150 m unshielded, 500 m shielded — enough for a small machine cell or conveyor section without a repeater.
Memory and backup strategy
The program and DB 1 data reside maintenance-free on integral EEPROM — no battery needed for program retention. Current DB 1 values, retentive memory bits, timers, and counters are buffered by a high-performance capacitor (min. 8 h at 40 °C, typ. 50 h). An optional battery module extends backup to 200 days. Four high-speed counters (32-bit, 30 kHz each) can be used as up/down counters or for connecting two incremental encoders with 90° offset A/B signals at up to 20 kHz. Each counter has parameterizable enable/reset and interrupt-on-setpoint capability.